3-D Chips Grow Up: In 2012, the chip will start to become the cube
The integrated circuit could use a lift. Almost 50 years after Gordon Moore forecast the path toward faster, cheaper chips, we’ve miniaturized electronic components so much that we’re increasingly colliding with fundamental physical limitations. The days of simple transistor scaling are long behind us—the latest, greatest chips are a hodgepodge of materials and design tweaks. These chips also leak a lot of power, and they contain transistors that are so variable in quality they’re difficult to run as intended.
Fortunately, chipmakers are pursuing a pair of innovations that will give dramatic boosts in the two categories that really count: performance and power consumption. In both cases, the trick will be to build up and into the third dimension. And manufacturers will do it at the level of both the individual transistor and the full microchip. In 2012, the chip will start to become the cube.
Until recently, microprocessor transistors have been flat, built into the plane of the silicon. Each field-effect transistor on a chip contains four parts: a source, a drain, a channel that connects them, and a gate on top that controls the current flow through the channel. Only the gate and a thin layer of insulator beneath it sit above the silicon.
But this past May, Intel unveiled its plans for the first big move away from the planar transistor. After months of gearing up production, the new transistors, which are built into a processor code-named Ivy Bridge, will make their way onto the market during the first half of 2012.
The switch to these pop-up transistors—often called FinFETs—helps tamp down one of the key problems that have emerged as engineers have shrunk transistor dimensions: leakage current. The smaller a transistor, the weaker the gate’s control and the easier it is for current to sneak across the channel when the transistor is supposed to be off. Intel decided to go with a design that turns the transistor channel on its side, creating a protruding fin between the source and drain that can be controlled by a gate on three sides instead of one.
Expanding into the third dimension will let chipmakers continue shrinking transistors to boost speed, without leaking power. Indeed, Intel estimates the 22-nanometer Ivy Bridge chips will be 37 percent faster at low voltage and draw less than half the power of the company’s 32-nm chips.
Intel’s 3-D leap was anticipated, but its timing still came as a surprise. “Moving the technology from the lab to the fab is a big deal,” says Tom Halfhill, a senior analyst at the Linley Group, in Mountain View, Calif. Based on available road maps, Halfhill says, other chipmakers working on FinFETs are a good four to five years behind Intel. “As far as we know, nobody else is close to volume production,” he says.
Intel’s FinFET isn’t the only foray out of Flatland. In 2012 there will be solid progress on an even more promising trick: stacking chips and wiring them together with interconnects that run straight down the stack, like elevator shafts in a skyscraper. If all goes well, this reworked interconnect technology could yield vastly faster and more efficient devices, no matter how chunky their transistors might be.